Hi,
Following is list of open positions for the ASIC organisation being built in Juniper, Bangalore.
Interested and eligible candidates can send their resume mentioning the position applied for.
Regards,
Jay Sharma
ASIC Manager (Design & verification):10+ yrs: We're looking for a visionary, high energy leader with hands on technical skills to build and lead India ASIC operations. The operations will consist of design and verification of ASICs and would involve leading design and verification teams to successfully complete block level/full chip design and verification and successfully deliver chip from specification to tapeout. Work with physical design and signal integrity teams to achieve timing closure in routed netlists. Need to make and maintain schedule. Ability to hire, retain and develop high performance teams.
Lead ASIC Verification Engineer: 6-10 yrs Lead verification team to successfully complete block/chip/system level verification. Perform ASIC verification for large, complex high-speed ASICs for Juniper's next generation of networking products. Develop detailed test plans, block and system-level test benches and verification environments, achieve complete coverage to ensure first working silicon. Develop functional models for System level architectural validation. Lead ASIC and system bring-up. Lead a team of engineers to successfully deliver chip from specification to tape out. Need to make and maintain schedule. Develop modeling/verificati on/coverage methodology. You will work closely with logic designers, software developers . Mentor junior engineers with the verification flow, strategy.
Lead ASIC Design Engineer : 6 -8 yrs Lead design team to successfully complete block level/full chip design. Develop architecture, micro-architecture and RTL implementation for ASIC's and systems for high-performance networking products.. Work with verification engineers to ensure first-time working silicon. Perform logic synthesis and timing analysis. Lead a team of engineers to successfully deliver chip from specification to tapeout. Work with physical design and signal integrity teams to achieve timing closure in routed netlists. Need to make and maintain schedule. Mentor junior engineers with design flow, strategy.
ASIC Verification Engineer : 5-7 yrs Responsible for block level/ full chip verification. Perform ASIC verification for large, complex high-speed ASICs for Juniper's next generation of networking products. Develop detailed test plans, block and system-level test benches and verification environments, achieve complete coverage to ensure first working silicon. Develop functional models for System level architectural validation. Assist in ASIC and system bring-up. You will work closely with logic designers, software developers.
ASIC Design Engineer :4 -6 yrs Responsible for block level/ full chip design. Develop micro-architecture and RTL implementation for ASIC's and systems for high-performance networking products. Work with verification engineers to ensure first-time working silicon. Perform logic synthesis and timing analysis. Work with physical design and signal integrity teams to achieve timing closure in routed netlists.
ASIC Design Engineer :3 -5 yrs Responsible for block level design. Develop micro-architecture and RTL implementation for ASIC's and systems for high-performance networking products. Work with verification engineers to ensure first-time working silicon. Perform logic synthesis and timing analysis.
ASIC Verification Engineer: 3+yrs Responsible for block level verification. Perform ASIC verification for large, complex high-speed ASICs for Juniper's next generation of networking products. Develop detailed test plans, block-level test benches and verification environments, achieve complete coverage to ensure first working silicon.You will work closely with logic designers.
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