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Tuesday, November 13, 2007

Openings in VLSI domain for 2+ exp people.


  
There are a few opeings in IC Design Services division in Sasken Comm.Check the details below. Please send the resumes to abhijeetbhalerao@ gmail.com
 
Hi friends , 
 
We have organised   SCHEDULED Recruitment Event  for   ICDS  on   17th Nov 2007 (Saturday) in Fac Z  starting at 9:30AM.  
The details are as follows:-
 
 

      

     VENUE : Fac   Z   (139/25, Ring Road, Domlur, Bangalore 560 071 

Domain :   ICDS -  Front End Verification 

Desired Qualification

BE/B..Tech/ME/ M.Tech/MS /MCA
Skills
  • Verification of a fullchip or Gate level verification, Formal Verification, Scripting, programming.
  • Experience in Verilog, VHDL, Modelsim or any Digital design simulator.
  • SOC Verification, Frontend verification Knowledge of VERA / SPECMAN is a big PLUS.
Experience

 2   to   6   years

   

Domain :   ICDS - Physical Design 

Desired Qualification

BE/B.Tech/ME/ M.Tech/MS /MCA 
Skills
  • Circuit Design, Simulation, transistor level, physical design/custom layout design, full chip, &R flow, place and route, clock tree synthesis, SI, physical verification- DRC/LVS/ERC.
  • Good backend design knowledge is an advantage.
  • CVS, Clearcase. Bug tracking tool usage , Standard cell library development , IO cell development, automation using Perl, understanding VHDL, Verilog, Usage of cadence and Synopsys suite of tools.
Experience

2   to   6   years

Domain :  ICDS - DFT  (Design-for- Testability) 

Desired Qualification

BE/B.Tech/ME/ M.Tech/MS /MCA
Skills
  • Synopsis DFT compiler, BSD compiler, Tetramax, Mentor.
  • MBIST, BIST, FASTSCAN.
  • Digital Design experience.
  • Internal Scan, Memory BIST, Boundary scan, JTAG, NAND tree.
  • Test vector generation, ATPG, post silicon verification.
  • Scripting - Perl, Tcl/ Tk.
  • Knowledge of synthesis, timing closure - STA and P&R flow.
Experience

 2   to   6   years


 



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